The present invention generally relates to microelectronic assemblies, and more specifically to components that facilitate connections between a microelectronic element such as a semiconductor chip, and an external circuit element such as a printed circuit board.
Connection components are typically used in combination with microelectronic elements such as semiconductor chips to facilitate electrical interconnections between semiconductor chips and external circuit elements. The reliability of the entire circuit typically depends upon the electrical connections between the chip, the connection component and the external circuit element.
Various attempts have been made to produce reliable connections between microelectronic elements such as semiconductor chips and external circuit elements. For example, certain preferred embodiments of commonly assigned U.S. Pat. No. 5,148,265, the disclosure of which is hereby incorporated by reference herein, disclose improved methods for connecting semiconductor chips to circuit elements. According to certain embodiments discussed in the '265 patent, a semiconductor chip is connected to a corresponding substrate through a connection component including a dielectric material. The semiconductor chip has a plurality of peripheral contacts positioned in a peripheral area of a front surface thereof and the connection component is formed with a plurality of connecting terminals, each of which is connected to a bonding terminal adjacent the periphery of the connection component. The connection component is supported by a compliant layer. The peripheral contacts of the semiconductor chip are connected to the terminals of the connection component by bonding a plurality of leads to the chip. In one embodiment, the lead-bonding operation uses wires which are bonded to bonding terminals on the periphery of the connection component and to the contacts of the chip. During a wire bonding operation, when downwardly directed forces are applied to the peripheral region of the connection component containing the bonding terminals, this peripheral regions flexes downwardly. In some instances, it has been determined that downward movement of the peripheral region of the connection component may impede the bonding of the wires and the bonding terminals.
Certain preferred embodiments of commonly assigned U.S. patent application Ser. No. 08/709,127, the disclosure of which is hereby incorporated by reference herein, disclose a structure for compliantly interconnecting semiconductor chips and supporting substrates while substantially obviating problems associated with thermal cycling. In one preferred embodiment, the semiconductor chip package includes a sheet-like substrate having one or more apertures extending from a first surface to a second surface of the substrate and conductive terminals which are contacted from the second surface of the substrate. The substrate further has conductive leads electrically connected to and extending from each terminal and across the one or more apertures. Each lead is connected to a bond pad on the opposite side of the aperture so that each lead has an expansion section within the aperture which is laterally curved with respect to the plane of the substrate. In certain preferred embodiments, the expansion sections laterally curve at least twice in opposite directions and in one particular embodiment create substantially “S” shaped lead portions. This structure allows the package to compensate for coefficient of thermal expansion (“CTE”) mismatch problems by allowing flexing and bending of the expansion sections of the leads within the one of more apertures. The expansion sections of the leads are typically encapsulated with a compliant encapsulant to provided added support for their bending and flexing motion during thermal cycling.
Commonly assigned U.S. patent application Ser. No. 08/516,645, filed Aug. 18, 1995, the disclosure of which is hereby incorporated by reference herein, discloses a microelectronic assembly including a connection component having oppositely facing first and second surfaces, a connecting terminal region and a bonding terminal region. The connection component has connecting terminals on the second surface in the connecting terminal region and has bonding terminals in the bonding terminal region. The assembly also includes a microelectronic element such as a semiconductor chip or other element having a front surface and having contacts on the front surface. The connection component overlies the front surface of the semiconductor chip with the second surface of the connection component facing upwardly away from the chip and with the first surface facing downwardly toward the chip. The connecting terminals are movable relative to the chip in vertical directions, whereas the bonding terminals are supported against such vertical movement. The connection component preferably comprises a thin, flexible layer, and a compliant layer disposed between the flexible layer and the chip for movably supporting the connecting terminal region. The assembly according to this aspect of the invention desirably also includes a reinforcing structure for reinforcing the bonding terminal region of the flexible layer against vertical movement towards the semiconductor chip. Subassemblies according to this aspect of the invention can be subjected to a bonding operation, such as a wire bonding operation, in which flexible conductors such as bonding wires are connected between the bonding terminals and the contacts on the chip. Because the bonding terminal region is reinforced, the bonding operation can be conducted efficiently. However, the finished assembly still provides the benefits associated with a compliantly mounted interposer, including testability and compensation for thermal effects during operation.
In certain preferred embodiments of commonly assigned U.S. patent application Ser. No. 09/520,320 filed Mar. 7, 2000, the disclosure which is hereby incorporated by reference herein, disclosed a method of making a microelectronic package including an expandable structure. The method includes providing first and second microelectronic elements having electrically conductive parts, and providing an expandable structure between the microelectronic elements. The electrically conductive parts of the first and second microelectronic elements are then connected together so that they microelectronic elements are electrically interconnected. The expandable structure is then expanded after the connection step so that the microelectronic elements move away from one another. The expandable structure is substantially rigged before the expanding step and substantially compliant after the expanding step. During the expanding step, the expandable structure remains in contact with the microelectronic elements and the microelectronic elements remain electrically interconnected. Thus, the '320 patent application allows or provides a rigged structure during bonding of electrically conductive parts, whereby the rigged structure maybe transformed into a compliant structure after the bonding steps have been completed.
In spite of the improved methods described above for connecting a semiconductor chip and an external circuit element, further improvements would be desirable.